An integrated circuit contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information. Within an integrated circuit, metal layers are stacked on top of one another using intermetal or interlayer dielectric layers that insulate the metal layers from each other. Normally, each metal layer must form an electrical contact to at least one additional metal layer. Such electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers, and filling the resulting via with a metal to create an interconnect structure. Metal layers typically occupy etched pathways in the interlayer dielectric. A “via” normally refers to any recessed feature such as a hole, line or other similar feature formed within a dielectric layer that provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer. Similarly, recessed features containing metal layers connecting two or more vias are normally referred to as trenches.
A long-recognized objective in the constant advancement of integrated circuit (IC) technology is the scaling down of IC dimensions. Such scale down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of ICs. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. These advances are driving forces to constantly scale down IC dimensions. An increase in device performance is normally accompanied by a decrease in device area or an increase in device density. An increase in device density requires a decrease in via dimensions used to form interconnects, including a larger aspect ratio (i.e., depth to width ratio). As the minimum feature dimensions on patterned substrates (wafers) steadily decreases, several consequences of this downward scaling are becoming apparent. For example, the recessed features are becoming so small that voids in bulk metal filling of the recessed features are unacceptable. As the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, electromigration failure, which may lead to open and extruded metal lines, is now a well-recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistivity increases substantially, and this increase in line resistivity may adversely affect circuit performance.
The introduction of Cu metal into multilayer metallization schemes for manufacturing integrated circuits is enabled by the damascene Cu plating process and is now extensively used by manufacturers of advanced microprocessors and application-specific circuits. However, Cu metal cannot be put in direct contact with dielectric materials since Cu metal has poor adhesion to the dielectric materials and Cu is known to easily diffuse into common integrated circuit materials such as silicon and dielectric materials where Cu is a mid-bandgap impurity. Furthermore, oxygen can diffuse from an oxygen-containing dielectric material into Cu, thereby decreasing the electrical conductivity of the Cu metal. Therefore, a diffusion barrier material is formed on dielectric materials and other materials in the integrated circuits to surround the Cu metal and prevent diffusion of the Cu into the integrated circuit materials.
A tantalum nitride/tantalum (TaN/Ta) bilayer is commonly used as a diffusion barrier/adhesion layer for Cu metallization since the TaN barrier layer adheres well to oxides and provides a good barrier to Cu diffusion and the Ta adhesion layer wets well to both TaN on which it is formed and to the Cu metal formed over it. However, Ta is normally deposited by sputtering or plasma processing methods which are unable to provide conformal coverage over high aspect ratio recessed features. Ruthenium (Ru) has been suggested to replace the Ta adhesion layer since it may be conformally deposited and it adheres well to TaN and to Cu metal. However, Cu metallization structures containing Ru metal films have generally showed higher Cu resistivity than those containing the traditional TaN/Ta bilayers and oxidation of the Ru metal films during processing can result in voids and incomplete bulk Cu metal fill in the recessed features, thereby increasing the electrical resistance and adversely affecting the reliability of the semiconductor device.
Therefore, new processing methods are needed for forming low-resistivity film structures containing bulk Cu metal and Ru metal films.